1. Field of the Invention
The present invention relates to a wireless apparatus or device suitable for use in a wireless communication system using a TDMA (Time Division Multiple Access) system, and particularly to a receiving circuit.
This application is a counterpart of Japanese patent application, Serial Number 306102/2000, filed Oct. 5, 2000, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
As shown in FIG. 7(a), a receiving circuit suitable for use in a wireless communication system using a TDMA mode or system receives burst signals every predetermined time intervals (corresponding to 5 msec while a call is in progress and integral number times of 5 msec while no call is in progress). Each of the burst signals comprises a frame. The length of the frame is 625 μsec. A structure of the frame for each burst signal will now be explained using the drawings. FIGS. 7(b) and 7(c) are respectively diagrams showing structures of frames. The frame structures shown in FIGS. 7(b) and 7(c) are identical to each other. The frame structure will be described below using FIG. 7(b). The frame has a preamble part 701, a synchronous pattern part 702 which follows the preamble part 701, a data part 703 which follows the synchronous pattern part 702, and an error detecting data part 704 (hereinafter called CRC data part 704) which follows the data part 703. Further, the frame has a control data part such as a guard bit, etc. However, they will be omitted for convenience of explanation.
The preamble part 701 stores therein initial phase pulling-in information (hereinafter called phase information) for allowing a burst signal received from the transmitting side by the receiving side to be normally captured. The synchronous pattern part 702 stores therein synchronous pattern information (hereinafter called synchronous information) for detecting (also called capturing) the synchronism of the burst signal received by the receiving side. The data part 703 stores transmit-receive information (hereinafter called data) therein. The CRC data part 704 stores therein error-correcting code information for effecting error detection/correction on the burst signal.
Meanwhile, the conventional receiving circuit has properly detected synchronous information stored in a synchronous pattern part of a currently receiving burst signal to thereby determine a timing provided to store data of a data part of the currently receiving burst signal and has stored the data of the data part therein.
However, the conventional receiving circuit has a problem in that since a preamble part is located in a stage preceding the synchronous pattern part storing the synchronous information therein even if the synchronous information is properly detected, the timing provided to store phase information stored in the pre-stage preamble part cannot be determined.
The conventional receiving circuit also has a problem in that even if synchronous information is detected from a previously-received burst signal, the result of detection is not used for storing a burst signal to be next received.
Further, a bit error rate characteristic can be obtained by measuring the degree of an error in data with the ratio (C/N ratio) between a radio signal and noise as a parameter. Therefore, the bit error rate characteristic cannot properly be measured where the synchronous information cannot be detected. Thus, when the synchronous information is erroneously detected, the data cannot be stored and hence a bit error rate leads to about 50%. Accordingly, a problem arises in that the bit error rate cannot be measured accurately.